Anirudh Devgan, CEO of Cadence, highlighted that the company’s AI-enhanced chip design tools achieve performance and density gains akin to advancing to a new process node, without the physical transition. He noted impressive improvements in power, performance, and area (PPA), alongside productivity boosts ranging from 5x to 10x. Cadence’s AI tools have reportedly delivered customers a 5% to 20% increase in PPA, driving significant efficiency in chip design and manufacturing.
Anirudh Devgan, PDG de Cadence, a souligné que les outils de conception de puces assistés par l’IA de l’entreprise permettent d’obtenir des gains de performance et de densité similaires à ceux d’une nouvelle étape de procédé, sans la transition physique. Il a noté des améliorations impressionnantes en termes de puissance, de performance et de surface (PPA), ainsi que des gains de productivité allant de 5 à 10 fois. Les outils d’IA de Cadence auraient permis à ses clients d’obtenir une augmentation de PPA de 5 % à 20 %, entraînant une efficacité significative dans la conception et la fabrication de puces.
Anirudh Devgan, the CEO of Cadence, recently pointed out that the company’s AI-enhanced chip design tools provide performance and density improvements comparable to those achieved by transitioning to a next-generation process node, all without the need for an actual node change. Devgan highlighted significant gains in performance, power, and area (PPA) improvements—key metrics for semiconductor manufacturers—and noted remarkable productivity boosts, particularly with the company’s custom processors.
In discussing the latest suite of AI-assisted software tools from the EDA company, Devgan stated, « Overall, we are excited about the benefits we’re witnessing, particularly with PPA enhancements. Productivity improvements can range from five to ten times, and the PPA advantages are truly outstanding, virtually akin to a node upgrade. A typical process node transition yields a PPA improvement of around 15% to 20%, and we can achieve that using AI. »
« As you may know, we offer a robust Cadence.AI portfolio with five major AI platforms: analog, digital, verification, PCB, and package and system analysis, » Devgan explained during a conference call with analysts and investors. « Customers frequently report PPA improvements ranging from 5% to 20%, which is substantial. »
Modern process technologies tend to offer limited performance and transistor density improvements from one node to another. For instance, TSMC’s N5 (5nm-class process) achieves a performance boost of 10% to 15% over its N3 (3nm-class node), while a similar enhancement is anticipated for the upcoming N2 in relation to N3. Thus, securing up to a 20% performance increase through a suite of AI-optimized tools represents a significant achievement comparable to advancing to a new process node.
Cadence is widely recognized for its electronic design automation (EDA), simulation, and prototyping software aimed at chip development. However, it’s less known that the company also designs its own Palladium processors, among the most intricate chips produced by TSMC, specifically to boost simulation workloads. Enhancing the performance and increasing the transistor density of these Palladium processors is critical for Cadence’s competitive edge and cost management, prompting the company to utilize its own tools to optimize these processors.
« We are also implementing our solutions internally,” Devgan added. “These comparisons clearly showcase the differences between AI and non-AI solutions. For example, in the recent Palladium Z3 chip, we observed about a 15% power improvement using Cadence Cerebrus. In our latest AI IP designs, we achieved improvements ranging from 13% to 20% in our IP group with Cadence.AI solutions, aligning closely with results from our key customers. »
In addition to PPA enhancements, Cadence asserts that its AI tools significantly boost productivity, typically achieving between five to ten times the regular output. Should this level of efficiency prove consistent, the Cadence.AI portfolio could become an exceptionally attractive option for an industry that must produce more advanced designs, delivering greater performance while also controlling costs.
Anirudh Devgan, PDG de Cadence, a récemment déclaré que les outils de conception de puces assistés par l’IA de l’entreprise permettent des améliorations de performance et de densité des puces similaires à celles d’une transition vers un nœud de processus de nouvelle génération, mais sans nécessiter un changement de nœud. Devgan a cité d’importantes améliorations des performances, de la puissance et de l’aire (PPA), qui sont des indicateurs clés pour les fabricants de semi-conducteurs, ainsi que des augmentations de productivité considérables, notamment avec les propre processeurs personnalisés de l’entreprise.
En discutant de la dernière suite d’outils logiciels assistés par l’IA de l’entreprise EDA, Devgan a déclaré : « Dans l’ensemble, nous sommes ravis des bénéfices que nous constatons, notamment en ce qui concerne les améliorations de PPA. Les augmentations de productivité peuvent varier de cinq à dix fois, mais les avantages en matière de PPA sont vraiment remarquables et presque équivalents à un changement de nœud. Un changement de nœud de processus classique engendre généralement une amélioration de 15 % à 20 % de la PPA, et nous pouvons atteindre cela grâce à l’IA. »
« Comme vous le savez peut-être, nous proposons un portefeuille Cadence.AI riche avec cinq grandes plateformes IA : analogique, numérique, vérification, PCB et analyse de systèmes et de paquets », a expliqué Devgan lors d’une conférence téléphonique avec des analystes et des investisseurs. « Nos clients constatent fréquemment des améliorations en PPA allant de 5 % à 20 %, ce qui est